Advanced knowledge of SystemVerilog for RTL design and verification. Used extensively in undergraduate projects and during my internship at Dynamic Solution Innovators for RISC-V processor design.

Proficient in MATLAB for signal processing, control systems, and simulation. Used in numerous coursework projects throughout my undergraduate studies at BUET.

Used Python for hardware verification, automation, and data analysis. Applied in my undergraduate thesis for simulating quantum circuits and during my internship for verification scripts.

Experienced with assembly language programming for microprocessors and microcontrollers. Worked with RISC-V assembly during my industrial attachment program.

Used C for embedded systems programming and TCL for EDA tool automation. Applied in various hardware design and verification projects.

Worked with Qiskit for quantum circuit design and simulation as part of my undergraduate thesis on "Design of Stabiliser Encoder Frameworks and Steane Code Performance Analysis".

Proficient with Vivado Xilinx for FPGA design, implementation, and verification. Used extensively during my industrial attachment at Dynamic Solution Innovators.

Used Cadence Virtuoso for analog circuit design and simulation, particularly during the National Analog Design Competition (VLSITHON 2.0).

Experience with FPGA-based design implementation and testing, including work with Xilinx FPGA boards for digital system design projects.

Used PSpice and Proteus for circuit simulation and PCB design in various electronics courses and projects at BUET.

Basic knowledge of Cadence Genus and Innovus for digital design synthesis and place-and-route in ASIC design flow.

Experience with Intel Quartus for FPGA design targeting Intel/Altera devices in various digital design projects.