Hello, I'm

Anindya Kishore Choudhury

Recent Graduate
Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology (BUET)
Dhaka, Bangladesh

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About Me

I'm Anindya Kishore Choudhury, an engineer and researcher passionate about computer architecture, VLSI design, and hardware–software co-design. I work at Caspia Technologies (FL, USA), focusing on hardware verification and design automation. I began by verifying open-source cryptographic IP cores and DDR memory controllers, building automated verification pipelines, and optimizing FPGA toolchains. Currently, I integrate memory models with RISC-V RV64G cores, explore cache architectures, and validate processor behavior.

My research aims to make chip design more reliable and private through AI-assisted verification. I develop frameworks to automatically analyze RTL code and assist engineers in debugging while maintaining data privacy. My undergraduate thesis focused on quantum error correction, designing encoders for Steane codes and evaluating concatenated ECC performance in one-way quantum repeaters.

I also serve as a Lecturer in Electrical and Electronic Engineering, teaching microprocessors, electronics, and communication engineering, and mentoring students through hands-on design projects. My goal is to create intelligent, secure, and efficient hardware systems that bridge computation and automation.

Research Interests

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Computer Architecture

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DL/ML Accelerator Design

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VLSI Computer-Aided Design

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Hardware Security

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RISC-V ISA/Processor Design

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Trustworthy ML

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Hardware Verification

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Neuromorphic Computing

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Energy-efficent Electronics

Latest Updates

News

Jul 2025
I am hired by Caspia Technologies (FL, USA) through their Bangladeshi partner Tecknoz as a remote engineer.
Jul 2025
I joined Ahsanullah University of Engineering and Technology as an Adjunct Lecturer in the EEE department.
May 2025
I joined Presidency University as a Lecturer in the EEE department.
Mar 2025
Completed the requirements for Bachelor of Science Degree in EEE from BUET.
Jan 2025
Successfully defended my undergraduate thesis on "Design of Stabiliser Encoder Frameworks and Steane Code Performance Analysis".
Dec 2024
Secured First Runners Up position in the National Analog Design Competition (VLSITHON 2.0).
Jun 2024
Designed and verified a RISC-V processor at Dynamic Solution Innovators Limited as part of the industrial internship.
Jul 2024
Awarded University Merit Scholarship for Securing GPA: 4.00/4.00 in the 7th Semester.
Dec 2023
Awarded University Merit Scholarship for Securing GPA: 3.96/4.00 in the 6th Semester.
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