Advanced knowledge of SystemVerilog for RTL design and verification. Used extensively in undergraduate projects, industrial attachment at Dynamic Solution Innovators for RISC-V processor design, and currently at Tecknoz/Caspia Technologies for developing testbenches and verification infrastructure for CVA6 processor core.

Proficient in Verilog HDL for digital design and FPGA implementation. Core language for hardware description in academic and industry projects, including verification of 100+ cryptographic IP cores.

Experience with VHDL for digital system design and verification in coursework and projects.

Used SystemC for system-level modeling and hardware-software co-design during industrial attachment.

Used Python extensively for hardware verification automation, test data extraction scripts, build pipeline automation at Tecknoz, data analysis, and quantum circuit simulation in thesis work.

Proficient in C for embedded systems programming, low-level hardware interfacing, and RISC-V bare-metal programming.

Experience with C++ for algorithm development and object-oriented design in hardware verification frameworks.

Proficient in MATLAB for signal processing, control systems, and simulation in numerous coursework projects at BUET.

Experienced with MIPS and RISC-V assembly language programming for microprocessors during industrial attachment. Currently writing comprehensive RISC-V assembly test programs for RV32I instruction set verification at Tecknoz, covering arithmetic, logical, branch, load/store, and system instructions.

Used TCL for EDA tool automation, scripting synthesis flows, design constraint management, and FPGA toolchain configuration.

Proficient in Shell scripting for build automation, verification workflows, toolchain management, and Linux system administration at Tecknoz.

Working knowledge of HTML, CSS, and JavaScript for documentation, dashboards, and web-based tools.

Proficient with Xilinx Vivado for FPGA design, implementation, and verification. Used extensively during industrial attachment at Dynamic Solution Innovators and currently at Tecknoz for simulating RISC-V processor designs and running RTL verification testbenches.

Used Cadence Virtuoso for analog circuit design and simulation, particularly during the National Analog Design Competition (VLSITHON 2.0).

Experience with Cadence Genus for logic synthesis in ASIC design flow, optimizing for PPA metrics.

Used Cadence Innovus for physical design implementation including placement, routing, and timing closure.

Experience with Cadence Xcelium for advanced verification and simulation of complex digital designs at Tecknoz.

Proficient with ModelSim for HDL simulation and debugging in academic and industry projects.

Used QuestaSim for advanced verification features including coverage analysis and assertion-based verification.

Experience with GHDL open-source VHDL simulator for verification in open-source toolchain workflows at Tecknoz.

Proficient with Synopsys VCS for industry-standard RTL simulation and verification at Tecknoz/Caspia Technologies, ensuring cross-platform compatibility.

Used Verilator extensively for fast open-source Verilog simulation, cycle-accurate modeling, and migrating legacy testbenches to open-source simulators at Tecknoz.

Experience with FuseSoC for managing IP cores and automating multi-tool FPGA/ASIC workflows at Tecknoz, streamlining build processes across different toolchains.

Proficient with Spike RISC-V ISA simulator for golden reference modeling at Tecknoz. Used to generate expected execution traces for validating CVA6 processor RTL implementation, comparing instruction-by-instruction behavior to ensure ISA compliance.

Experience with FPGA-based design implementation and testing, including work with Xilinx and Intel FPGA boards for digital system design projects and processor verification.

Used Raspberry Pi for embedded systems projects including autonomous fire detection robot with YOLOv5.

Experience with STM32L4 microcontroller for embedded systems development, currently establishing lab at Presidency University.

Used ESP32 for IoT-enabled projects including smart walking stick with fall detection and real-time alerts.

Extensive experience with RISC-V ISA through processor design internship at Dynamic Solution Innovators Ltd. and current role at Tecknoz. Deep understanding of RV32I/RV64I instruction sets, assembly programming, and ISA compliance verification.

Currently working on CVA6 (Ariane) RISC-V processor core verification at Tecknoz. Developed comprehensive instruction-level tests, designed RTL testbench infrastructure with AXI memory models, and implemented automated validation framework comparing RTL execution against Spike ISA simulator.

Strong understanding of CPU architecture including pipelining, out-of-order execution, branch prediction, memory hierarchy, cache coherence, and instruction set design from coursework, processor design projects, and industry verification experience.

Knowledge of ASIC design flow from RTL to GDS including synthesis, place-and-route, timing closure, and PPA optimization.

Proficient in functional simulation for verifying design correctness before synthesis and implementation. Experience with both directed and constrained-random testing methodologies.

Experienced in developing comprehensive testbenches with constrained-random stimulus, coverage-driven verification, and assertion-based verification. Currently designing testbench infrastructure for CVA6 processor including AXI memory models and automated result validation.

Specialized in ISA-level processor verification at Tecknoz. Develop instruction-level test programs in RISC-V assembly covering all instruction categories, validate processor behavior against architectural specifications, and ensure ISA compliance through systematic testing.

Expert in golden reference validation methodology using Spike ISA simulator. Automated comparison of RTL execution traces with golden model outputs, detecting functional discrepancies, validating register updates, memory operations, and control flow behavior instruction-by-instruction.

Knowledge of High-Level Synthesis for converting C/C++ algorithmic descriptions to RTL implementations.

Experience with static timing analysis for ensuring timing closure and meeting performance requirements.

Proficient in build automation using Makefiles, Python scripts, and CI/CD pipelines for verification workflows at Tecknoz. Developed unified RTL verification framework automating compilation, simulation, and validation across multiple toolchains.

Experience with AXI4 protocol for high-performance memory-mapped communication. Designed and integrated AXI4 memory models for CVA6 processor testbench, handling burst transactions, out-of-order responses, and multi-master arbitration.

Working knowledge of AXI-Lite protocol for simple memory-mapped register access. Used in peripheral interface design and processor verification infrastructure.

Proficient with Linux command-line interface for development, debugging, server administration, and managing verification workflows in remote development environments.

Expert in Makefile development for complex hardware verification workflows. Built automated build systems handling multi-stage compilation (RTL and Spike binaries), simulation execution, result extraction, and comparison at Tecknoz.

Used Jupyter notebooks for interactive development, data analysis, and documentation in research projects.

Proficient with Git version control for collaborative development, managing 60% of pull requests during RISC-V internship, and maintaining verification infrastructure codebases.