My Research Journey

Research Experience

LLM-Aided Verification Research

LLM-Aided Test Case Generation for SoC Design

Ongoing
Mar 2025 - Present Hardware Verification

Bangladesh University of Engineering & Technology (BUET)

Supervisor: Prof. Dr. Anindya Iqbal, CSE, BUET

Developing an intelligent offline verification assistant for System-on-Chip design using Large Language Models. The project focuses on automating comprehensive test case generation while maintaining complete data privacy for chip design companies through on-device deployment of quantized models.

Key Contributions

  • Built comprehensive RTL code database for model training
  • Trained 7B-parameter quantized model using knowledge distillation
  • Developed offline verification assistant ensuring data privacy
Python SystemVerilog LLM Fine-tuning Quantization
Quantum Error Correction Research

Stabiliser Encoder Design & Steane Code Analysis

Completed
Jan 2024 – Mar 2025 Quantum Computing

Undergraduate Thesis, Bangladesh University of Engineering and Technology (BUET)

Supervisor: Prof. Dr. Sajid Muhaimin Choudhury, EEE, BUET

Extended an existing one-way quantum repeater architecture by developing a general stabiliser encoder framework capable of producing logical |0⟩L and |1⟩L states for any stabiliser code. Applied the framework to implement and evaluate the Steane [[7,1,3]] code as an alternative outer code, analyzing its transmission efficiency and fault tolerance for long-distance quantum communication.

Key Contributions

  • Encoder Framework: Designed and implemented a universal stabiliser encoder pipeline — converting stabilisers to binary matrices, applying RREF to obtain standard form, and constructing projector-based logical states verified by eigenstate conditions (Algorithms 4–8).
  • Automated Correction Tables: Developed Python algorithms to automatically generate Steane [[7,1,3]] correction lookup files: 384 flagged entries (6×64) and 448 erasure cases (7×64), removing manual dependence for syndrome enumeration.
  • Repeater Integration & Analysis: Integrated encoded Steane logical qubits into an existing concatenated one-way repeater model to compute SKR, ηe, Σptrans, and cost metrics. Found that Steane performs slightly worse at εr=0.01% but drastically better for εr>0.01% (SKR ≈10³ at 10,000 km compared to ≈10² for the [[5,1,3]] baseline).
  • Simulation Pipeline: Built a reproducible workflow producing binary output for postprocessing in Mathematica; the complete Steane simulation and data analysis ran for ~35 hours after optimization.

Impact

  • Provides a general encoder automation toolkit for benchmarking stabiliser codes in concatenated repeater networks.
  • Demonstrates that the Steane [[7,1,3]] code offers higher robustness at εr > 0.01%, enabling more reliable long-distance quantum links even with moderate gate errors.
  • Outlines extensions for GPU-based simulation and exploration of larger codes ([[8,3,3]], [[11,1,5]]) to scale future repeater studies.
Python MATLAB C++ Mathematica Quantum Circuits Error Correction

Browse My

Significant Projects

AXI Memory Verification Architecture
AXI Memory Verification Simulation

AXI4 Memory Subsystem Verification for RISC-V

Built complete AXI4 protocol verification environment for Ariane (CVA6) RISC-V core memory controller. Implemented concurrent channel operation (AW/W/B/AR/R) with proper handshake synchronization, fixing critical missing W_READY handshake. Designed 9 comprehensive test scenarios covering byte to doubleword accesses (8/16/32/64-bit) with dynamic address alignment and randomized data patterns. Verified 512MB memory subsystem through 150+ transactions, validating complete RTL stack from axi_ram through protocol converters to memory array. Achieved production-grade verification with 100-cycle timeout protection and automated pass/fail reporting.

RISC-V Branch Test Architecture
Spike ISA Simulator Integration

RISC-V Branch Instruction Verification Suite

Developed comprehensive verification framework for all 6 RISC-V conditional branch instructions (BEQ/BNE/BLT/BGE/BLTU/BGEU) with 284 systematic test cases. Implemented automated Spike ISA simulator integration for golden reference generation, extracting memory write traces from execution logs for hardware validation. Designed 13 test categories per instruction covering boundary values (max/min signed/unsigned), equality/inequality conditions, signed vs unsigned semantic differences, register combinations, and data hazards. Verified complete branch behavior through marker-based result tracking (0x55/0x66 for pass, 0xAA/0xBB for fail) stored in dedicated data sections. Achieved full functional coverage with automated toolchain integration (GCC, objcopy, objdump) and production-ready Makefile workflow for RTL simulation environments.

16-bit Carry Lookahead Adder
16-bit Carry Lookahead Adder
16-bit Carry Lookahead Adder
16-bit Carry Lookahead Adder

16-bit Carry Lookahead Adder Design: From RTL to PPA

Designed RTL module, developed linear and layered testbenches, wrote TCL scripts for synthesis, and implemented SystemVerilog randomization for coverage testing. The project encompasses a complete ASIC design flow with detailed power, performance, and area (PPA) analysis.

Smart LED Panel Testing
Smart LED Panel Testing
Smart LED Panel Testing
Smart LED Panel Testing

Smart LED Panel Testing using Digital Sensing and Image Processing

Formulated project concept, created implementation blueprint, developed image processing algorithms, and automated reporting system. This system streamlines LED panel quality control by identifying defects through computer vision techniques.

Fire Detecting Robot
Fire Detecting Robot
Fire Detecting Robot
Fire Detecting Robot

Autonomous Fire Detection and Extinguishing Robot

Implemented YOLOv5 fire detection model on Raspberry Pi, configured real-time fire detection via webcam, and developed robot's fire search and navigation algorithms. The system autonomously locates and extinguishes fires for early intervention.

Smart Walking Stick
Smart Walking Stick
Smart Walking Stick

Smart Walking Stick with Fall Detection Algorithm

Conceptualized project idea, developed novel fall detection algorithm for ESP32 microcontroller, and implemented a real-time internet-based alert notification system. The design helps visually impaired users navigate safely with advanced obstacle detection.

Bandgap Voltage Generator
Bandgap Voltage Generator
Bandgap Voltage Generator
Bandgap Voltage Generator

Bandgap Reference Voltage Generator in Cadence Virtuoso

Designed a 0.9V Bandgap Voltage Generator using GPDK045 with impressive specifications: 45 ppm/°C temperature coefficient, 1mA output current capability, and maximum supply current of 0.17 mA. Investigated different architectures for optimal performance.

Hand Drawn Curve Converter
Hand Drawn Curve Converter
Hand Drawn Curve Converter

Hand Drawn Curve to Equation Converter

Developed MATLAB algorithm from scratch to extract curves from BMP images and generate corresponding polynomial equations through image processing techniques. The tool enables quick digitization of hand-drawn mathematical functions.

Fire Detection System
Fire Detection System
Fire Detection System

Design of Fire Detection System with Analog ICs

Simulated a 4-bit Analog to Digital Converter Circuit, designed 4-bit Magnitude Comparator Circuit and Timing Circuit. Assembled the project on breadboard and tested using AT-700 ADC Board to create a reliable fire detection system.

Intelligent Battery Charger
Intelligent Battery Charger
Intelligent Battery Charger
Intelligent Battery Charger

Design Verification of Intelligent Battery Charger

Built a Buck Converter Design in Proteus for Variable DC Operation and modelled microcontroller operation for auto-cut off feature. This smart charger design prevents overcharging and extends battery life through intelligent charging algorithms.