My Research Journey
Bangladesh University of Engineering & Technology (BUET)
Supervisor: Prof. Dr. Anindya Iqbal, CSE, BUET
Developing an intelligent offline verification assistant for System-on-Chip design using Large Language Models. The project focuses on automating comprehensive test case generation while maintaining complete data privacy for chip design companies through on-device deployment of quantized models.
Undergraduate Thesis, Bangladesh University of Engineering and Technology (BUET)
Supervisor: Prof. Dr. Sajid Muhaimin Choudhury, EEE, BUET
Extended an existing one-way quantum repeater architecture by developing a general stabiliser encoder framework capable of producing logical |0⟩L and |1⟩L states for any stabiliser code. Applied the framework to implement and evaluate the Steane [[7,1,3]] code as an alternative outer code, analyzing its transmission efficiency and fault tolerance for long-distance quantum communication.
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Built complete AXI4 protocol verification environment for Ariane (CVA6) RISC-V core memory controller. Implemented concurrent channel operation (AW/W/B/AR/R) with proper handshake synchronization, fixing critical missing W_READY handshake. Designed 9 comprehensive test scenarios covering byte to doubleword accesses (8/16/32/64-bit) with dynamic address alignment and randomized data patterns. Verified 512MB memory subsystem through 150+ transactions, validating complete RTL stack from axi_ram through protocol converters to memory array. Achieved production-grade verification with 100-cycle timeout protection and automated pass/fail reporting.
Developed comprehensive verification framework for all 6 RISC-V conditional branch instructions (BEQ/BNE/BLT/BGE/BLTU/BGEU) with 284 systematic test cases. Implemented automated Spike ISA simulator integration for golden reference generation, extracting memory write traces from execution logs for hardware validation. Designed 13 test categories per instruction covering boundary values (max/min signed/unsigned), equality/inequality conditions, signed vs unsigned semantic differences, register combinations, and data hazards. Verified complete branch behavior through marker-based result tracking (0x55/0x66 for pass, 0xAA/0xBB for fail) stored in dedicated data sections. Achieved full functional coverage with automated toolchain integration (GCC, objcopy, objdump) and production-ready Makefile workflow for RTL simulation environments.
Designed RTL module, developed linear and layered testbenches, wrote TCL scripts for synthesis, and implemented SystemVerilog randomization for coverage testing. The project encompasses a complete ASIC design flow with detailed power, performance, and area (PPA) analysis.
Formulated project concept, created implementation blueprint, developed image processing algorithms, and automated reporting system. This system streamlines LED panel quality control by identifying defects through computer vision techniques.
Implemented YOLOv5 fire detection model on Raspberry Pi, configured real-time fire detection via webcam, and developed robot's fire search and navigation algorithms. The system autonomously locates and extinguishes fires for early intervention.